Electric Tutorial

This tutorial will run through the design and simulation of a ‘plain vanilla’ positive edge triggered D flip-flop. Electric allows the design to be done and linked together through what are called facets. These facets are each different hierarchical levels of the design (i.e. Layout, schematic, VHDL, and so on). The design of this flip-flop will be covered in the transistor, schematic, VHDL, and layout levels. The purpose of this tutorial is to cover those topics that are not covered sufficiently in the provided User’s Manual. It is assumed that the student knows how to create a library and facets of that library.

Creating a Gate-Level Schematic Using Provided Logic Gates: We first created a digital schematic facet in the D Flip-Flop library using the digital gates provided in Electric. The schematic we used can be found in any basic logic design textbook. Placing a node (such as an “or” gate) on the schematic is done by the traditional click-and-place method (see manual).

Electric provides standard variable-input logic gates (and, or, xor, buffer). To negate inputs/outputs, click on the arc that connects to those nodes and select Arcs Negated. Simulation of Gate-Level Schematic: The simulation of the circuit can be done by selecting, Tools Simulation Simulate in the pull down menu. Please note that by simulating the circuit, the VHDL facet will automatically be created. A new window will open with a waveform for each port. To force the inputs, select the net by clicking on the name to the left. If the signal is a clock simple...

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