EDA Placement

ABOUT THIS CHAPTER Placement is the process of determining the locations of circuit devices on a die surface. It is an important stage in the VLSI design flow, because it affects routabil- ity, performance, heat distribution, and to a less extent, power consumption of a design. Traditionally, it is applied after the logic synthesis stage and before the routing stage. Since the advent of deep submicron process technology around the mid-1990s,

interconnect delay, which is largely determined by placement, has become the dominating component of circuit delay. As a result, placement information is essential, even in early design stages, to achieve better circuit per- formance. In recent years, placement techniques have been integrated into the logic synthesis stage to perform physical synthesis and into the architecture design stage to perform physical-aware architecture design. This chapter begins with an introduction to the placement stage. Next, vari- ous placement problem formulations are discussed. Then, partitioning-based approach,simulatedannealingapproach,andanalyticalapproachforglobalplace- ment are presented. After that, legalization and detail placement algorithms are described. The chapter concludes with a discussion of other placement approaches and useful resources to placement research. 11.1 INTRODUCTION Traditionally, placement is the design stage after logic synthesis and before rout- ing in the VLSI design flow. In logic synthesis, a netlist is generated. Then in placement, the locations of the circuit modules in the netlist are determined. After placement, routing is performed to lay out the nets in the netlist. Placement is a critical step in the VLSI design flow mainly for the following four reasons. First, placement is a key factor in determining the performance of a circuit. Placement largely determines the length and, hence, the delay of inter- connect wires. As feature size in advanced VLSI technology continues to reduce, interconnect delay has become the determining factor of circuit performance. 635 Interconnect delay can consume as much as 75% of clock cycle in advanced design. Therefore, a good placement solution can substantially improve the performance of a circuit. Second, placement determines the routability of a design. A well-constructed placement solution will have less routing demand (i.e., shorter total wirelength) and will distribute the routing demand more evenly to avoid routing hot spots. Third, placement decides the distribution of heat on a die surface. An uneven temperature profile can lead to reliability and timing problems. Fourth, power consumption is also affected by placement. A good placement solution can reduce the capacitive load because of the wires (by having shorter wires and larger separation between adjacent wires). Hence the switching power consumption can be reduced. In recent years, it has become essential for the logic synthesis stage to incor- porate placement techniques to perform physical design aware logic synthesis (i.e., physical synthesis). The reason is that without some placement informa- tion, it is impossible to estimate the delay of interconnect wires. Hence, given the significance...

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