DATE conference VHDL Tutorial - VHDL-2006-D3.0 Tutorial

V H D L - 2 0 0 6 - D 3 . 0 T u t o r i a l A g e n d a : Accellera Standards D ennis Brophy I E E E S t a n d a r d s E d w a r d R a s h b a V H D L T u t o r i a l J i m L e w i s A c c e l l e r a - V H D L - D 3 . 0 Fixed and Floating Point Packages W h a t s N e x t I n V H D L Q u e s t i o n s & A n s w e r s Accellera VHDL-2006-D3.0 By Jim Lewis, SynthWorks VHDL Training jim@synthworks.com S ynth W orks Accellera VHDL-2006-D3.0

O IEEE VASG - VHDL-200X effort O Started in 2003 and made good technical progress O However, no $$$ for LRM editing O Accellera VHDL TSC O Took over in 2005, O Funded the technical editing, O Users reviewed and prioritized proposals, O Did super-human work to finalize it for July 2006 * Accellera VHDL-2006-D3.0 * O Approved in July 2006 by Accellera board O Ready for industry adoption 2 Copyright © SynthWorks 2007 S ynth W orks Accellera VHDL-2006 O PSL O Expressions in port maps O IP Protection via Encryption O Read out ports O VHDL Procedural Interface - VHPI O Conditional and Selected O Type Generics assignment in sequential code O O Generics on Packages hwrite, owrite, … hread, oread O O Arrays with unconstrained arrays to_string, to_hstring, … O O Records with unconstrained arrays Sized bit string literals O O Fixed Point Packages Unary Reduction Operators O O Floating Point Packages Array/Scalar Logic Operators O O Hierarchical references of signals Slices in array aggregates O O Process(all) Stop and Finish O O Simplified Case Statements Context Declarations O O Don't Care in a Case Statement Std_logic_1164 Updates O O Conditional Expression Updates Numeric_Std Updates O Numeric_Std_Unsigned...

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